Optical-Electrical (O-E) interfaces are used in high speed communication systems to convert the incident light signal into an electrical signal. Typically, the O-E interface is made up of a photodiode (PD), to convert the incident light power into a current, and a Trans-Impedance Amplifier (TIA), to convert the photocurrent into a voltage of large enough amplitude to be managed by the following electronic stages. The TIA is generally followed by additional amplification stages to reach the desired output level and to drive the output load.
The TIA is typically considered an important block in high data rate (DR) applications since it ensures a large analog bandwidth (BW) in order not to degrade the Inter-Symbol Interference (ISI) of the received bit stream but, at the same time, it may desirably have a large enough gain to provide at its output a manageable voltage for the following stages. It should also typically maintain a low integrated noise at its output so as not to degrade the overall Signal-to Noise Ratio (SNR), that directly impacts the output Bit Error Rate (BER).
Two TIA architectures are typically used, the feedback one and the open-loop one. The feedback architecture makes use of an amplifying stage fed back in an inverting configuration and fed at the input by the PD photocurrent iPD (FIG. 1a). The feedback impedance ZT realizes the desired trans-impedance gain. On the other hand, the open-loop architecture realizes the desired trans-impedance gain by injecting the photocurrent directly into an impedance ZT, and uses an open-loop amplifier to increase the voltage level up to the desired level (FIG. 1b).
The feedback architecture is generally preferred in presence of large input capacitances because for a given input sensitivity and a desired BER it provides a larger BW. The advantage in terms of bandwidth (BW) directly depends on the gain A of the amplifying stage (e.g. this advantage can be quantified into a factor sqrt(A+1) in the most simplified model, assuming infinite BW and null output impedance for the amplifying stage). This advantage is achieved at the expense of a more complex architecture, that intrinsically dissipates a larger power, and that may be prone to non idealities and to stability issues. These effects may become more and more important as the data rate increases (typically >10 Gbps) due to high frequency parasitic effects. In addition, a large gain A at frequencies in the range of tens of GHz is generally difficult to achieve, especially in low supply amplifiers, and this may reduce or even nullifies the advantages of a feedback architecture.
To extend data rates beyond 10 Gbps, equalization techniques are typically used, and particularly feed-forward equalization based on inductive peaking (Mohan 2000). The purpose of these techniques is to enlarge the bandwidth of the amplifying stage by emphasizing specific frequency components of the received signal (typically the high frequency components), while maintaining unmodified the other spectral components. Depending on the amount of equalization needed, this operation can be either concentrated into a single stage (typically the TIA) or distributed over several stages of the receiver chain. In most applications a programmable equalization is used, to ensure proper operation and/or uniform performance over Process Voltage and Temperature (PVT) conditions.
FIGS. 1a and 1b show typical TIA topologies with a single-ended PD connection. However, a differential topology has been recently proposed and applied to an open-loop TIA architecture (FIG. 2) (Kucharsky 2010).
This topology may be particularly suitable for silicon photonics applications: in fact, these can make use of a balanced waveguide PD integrated on the same silicon substrate as the electronic circuits (or on a separate silicon substrate, similar to the one used for electronic circuits). A differential topology intrinsically offers two advantages compared to a single-ended one: a 3 dB better SNR and a higher rejection of supply noise. The topology proposed in (Kucharsky 2010) implements the desired trans-resistance using two equal resistances RT, PD, connected to VPD+ and VPD− respectively to properly bias the PD, and AC-coupled to the following stage, as shown in FIG. 2, to allow proper bias of the stage itself (typically implemented by a differential pair). However this topology faces intrinsic limits discussed below, especially when extended to high DR applications.
1) Even if the topology is differential, the PD generated photocurrent is forced over a single-ended path through the two RT,PD trans-resistances before being converted into a differential voltage. This may be undesirable at frequencies in the range of tens of GHz, since the path between VPD+ and VPD− is generally a good short circuit only at low frequencies, but it is not well characterized at frequencies in the range of tens of GHz. This effect can be modeled by two parasitic impedances ZPD1,2 in series with RT,PD, as shown in FIG. 3.
2) Any undesired noise coupled on the PD supplies can significantly degrade the jitter performance at the TIA output.
3) Any asymmetry in the values of the two ZPD1,2 impedances moves the behavior of the circuit far from the ideal balanced one.
4) If the photodiode (PD) is not integrated on the same die of the TIA, this topology may suffer from the parasitic capacitances added at the PD anode/cathode by the interconnects between the PD and the TIA. In particular, this topology may not allow simple implementation of ESD protection (that may be required if the PD is not integrated on the same die of the TIA), without penalizing the BW.
5) The latter issue (4) is hard to address in this topology when implementing a programmable equalization operation joined with the trans-impedance operation. Therefore the equalization operation is carried out in the amplifying stage following the trans-resistance. The reason is that programmable peaking uses active components, that are unavoidably asymmetrically biased due to the asymmetric connection of RT,PD (to VPD+ and VPD−, respectively). For example, in a CMOS implementation this means that PMOS transistors are used on one branch and NMOS transistors on the other one, and this, in turn, may lead to higher mismatches between the two branches, especially over PVT variations.